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Summary

Highly motivated Computer Engineer with 6 years of experience in designing, developing, and optimizing complex hardware and software systems. Proven expertise in full-stack embedded system development, from initial concept to deployment, with a strong focus on performance and reliability. Adept at bridging the gap between hardware and software to deliver innovative solutions in fast-paced technology environments.

Experience

Senior Computer EngineerNVIDIA
Santa Clara, CASep 2021Present
  • Led the design and verification of critical IP blocks for next-generation GPU architectures, reducing simulation time by 25%.
  • Optimized embedded firmware for a new inference engine, improving performance by 15% and reducing memory footprint by 10%.
  • Collaborated with cross-functional teams to integrate hardware and software components, successfully bringing 2 new products to market ahead of schedule.
  • Developed automated test benches in SystemVerilog, identifying and resolving over 50 complex hardware bugs pre-silicon.
Computer EngineerIntel Corporation
Folsom, CAJul 2018Aug 2021
  • Designed and implemented firmware for embedded controllers in server platforms, reducing boot-up time by 200ms across product lines.
  • Developed diagnostic tools in Python for hardware validation, decreasing debug cycles by 30% for new silicon.
  • Contributed to the architectural definition of power management units, achieving a 15% reduction in idle power consumption.
  • Performed extensive hardware/software integration testing, ensuring 99.9% reliability for critical system functions.

Projects

Education

Stanford UniversityM.S. in Computer Engineering
Stanford, CASep 2016Jun 2018
  • Specialized in VLSI Design and Embedded Systems, maintaining a 3.9 GPA.
  • Researched novel low-power CPU architectures, resulting in a published conference paper.
  • Awarded the Dean's Fellowship for academic excellence and research potential.
University of California, BerkeleyB.S. in Electrical Engineering (Computer Engineering focus)
Berkeley, CASep 2012May 2016
  • Graduated Summa Cum Laude with a 3.85 GPA.
  • Developed an FPGA-based image processing accelerator for a senior design project, achieving a 3x speedup.
  • Member of Eta Kappa Nu (Electrical Engineering Honor Society).

Skills

Hardware Design
VerilogVHDLSystemVerilogASIC/FPGA DesignPCB DesignEagleAltium DesignerLogic AnalyzersOscilloscopes
Software Development
CC++PythonAssembly (ARM, x86)Linux KernelRTOS (FreeRTOS, Zephyr)Embedded CDebugging (GDB, JTAG)
System Architecture
Microcontroller/Microprocessor SystemsSoC DesignMemory SubsystemsI/O Interfacing (SPI, I2C, UART)Networking ProtocolsPower Management
Tools & Methodologies
GitJiraConfluenceAgile/ScrumJenkinsDockerBash ScriptingVersion ControlTest-Driven Development