Michael Harris | Senior Design Verification Engineer at NXP Semiconductors

Summary

Senior Design Verification EngineerNXP Semiconductors

Austin, TXJul 2020Present

Led verification efforts for a high-performance automotive microcontroller SoC, achieving 100% functional coverage and reducing critical bugs by 25% prior to tape-out.
Architected and implemented a scalable UVM testbench framework for complex IP blocks, enabling 30% faster verification cycles across multiple projects.

Design Verification EngineerTexas Instruments

Dallas, TXJul 2018Jun 2020

Designed and implemented UVM test environments for mixed-signal power management ICs, leading to the successful verification of 3 new products.
Developed comprehensive verification plans and functional coverage models, achieving over 95% code coverage and 90% functional coverage on critical modules.

Developed a comprehensive UVM testbench for a multi-channel, high-speed NoC fabric, achieving 98% functional coverage within tight project deadlines.

Power Management Unit (PMU) Formal Verification

Nov 2019May 2020

Applied formal verification techniques to ensure correctness of a complex PMU IP, identifying deadlocks and unreachable states that simulation missed.
Developed SVA sequences for critical power-gating and clock-gating scenarios, proving robustness of the design under various power modes.

University of Texas at AustinMaster of Science in Electrical Engineering

Austin, TXAug 2016May 2018

Developed a novel constrained random test generation algorithm, improving bug detection efficiency by 15%
Completed thesis on formal verification techniques for power management units, achieving 98% coverage on example designs

Georgia Institute of TechnologyBachelor of Science in Electrical Engineering

Atlanta, GAAug 2012May 2016