Summary

Experience

Senior VLSI Design Engineer|NVIDIA

Santa Clara, CAAug 2021Present

• Led RTL design and integration for a critical GPU subsystem, reducing critical path delay by 12% and achieving targeted clock frequencies of 2.2 GHz.
• Developed and implemented power-saving techniques, including clock gating and power gating, leading to a 15% reduction in dynamic power consumption for complex IP blocks.

VLSI Design Engineer|Qualcomm

San Diego, CAJul 2018Jul 2021

• Designed and implemented high-speed digital circuits in Verilog for mobile SoC platforms, contributing to the successful launch of 3 flagship Snapdragon processors.
• Performed extensive static timing analysis (STA) and resolved over 200 timing violations, improving design robustness and meeting aggressive timing targets across multiple corners.

Projects

High-Performance RISC-V Processor Core

Mar 2021Sep 2022

• Designed a 5-stage pipelined RISC-V core in Verilog, achieving a peak frequency of 1.5 GHz on a 7nm process node.

Custom DDR4 Memory Controller

Jan 2019Dec 2019

• Architected and implemented a DDR4 memory controller IP for a custom SoC, optimizing for bandwidth and latency.

Education

Stanford University|M.S. in Electrical Engineering

Stanford, CASep 2016Jun 2018

• Specialized in Computer Architecture and VLSI Systems Design.
• Coursework included Advanced Digital Design, CMOS VLSI Design, and Design Verification.
• GPA: 3.9/4.0

University of California, Berkeley|B.S. in Electrical Engineering

Berkeley, CASep 2012May 2016

• Graduated Summa Cum Laude with a focus on Digital Integrated Circuits.
• Awarded department's Outstanding Senior Design Project for a custom RISC-V processor.
• GPA: 3.8/4.0

Publications

A Low-Power Clock Gating Scheme for High-Performance Processors

Aug 2020Mei Zhang, Chen Li, David Kim

Enhancing Timing Closure with Advanced Placement Algorithms in Sub-7nm ASICs

May 2019Mei Zhang, Alex Wong

SystemVerilog UVM-based Verification Methodology for Complex SoC Subsystems

Nov 2018Mei Zhang, Sarah Miller

Skills

RTL Design & Verification

VerilogSystemVerilogUVMVHDLAssertionsFunctional Coverage

EDA Tools

Synopsys VCSSynopsys Design CompilerSynopsys IC Compiler IICadence XceliumCadence GenusPrimetimeFormality

Physical Design

Static Timing Analysis (STA)Power AnalysisFloorplanningPlacement & RoutingClock Tree Synthesis (CTS)DRC/LVS

Scripting & Programming

PythonTCLPerlC++Shell ScriptingMakefiles

Digital Design

CMOSLow Power DesignASIC Design FlowFPGA PrototypingComputer ArchitectureSoC Design